always@(敏感信号)
always@(posedge rst)
begin
if(rst)
...
end
Copy
Verilog
always@(posedge rst)
begin
if(!rst)
...
end
Copy
Verilog
如果写成下面这种形式 编译报错.
Assignment under multiple single edges is not supported for synthesis
因为 posedge rst , 相当于去检测上升沿, 如果 此时再去判断 !rst 相当于又作边缘检测